In computer systems, interrupt signals are typically used by system devices to request service of a system processor. An interrupt is a suspension of a process, such as execution of a program by the processor, which is performed in such a manner that the process can be resumed. Typically, the interrupt is implemented as an instruction that directs the microprocessor to suspend what it is doing and run a specified routine. When the routine is complete, the microprocessor resumes it original operation.
Interrupts take several forms (e.g. first-level interrupts, second-level interrupts) which indicate the relative criticality or severity of the interrupt. A particularly critical interrupt is commonly known as a non-maskable interrupt (NMI). An NMI is a hardware interrupt which takes priority over interrupts generated by software or by the keyboard or other such system devices. An NMI cannot be overruled (masked) by another service request. Non-maskable interrupts are issued to the microprocessor only in disastrous circumstances such as severe memory errors or impending power failures. A microprocessor response to an NMI is typically referred to as a "hot restart" of the system.
Because non-maskable interrupts cannot be masked and thus particularly adversely affect system operation, timeout mechanisms are often used to determine if microprocessor operation should in fact be interrupted as a result of an NMI. Timeout mechanisms determine if certain events have occurred during a prescribed time period and output a signal based on whether or not the expected event occurs. Typically, the prescribed time period defines an interval in which the expected event is to occur, such as a response to polling or addressing, before system operation is interrupted and must then be restarted. For example, the system device which issued the non-maskable interrupt could clear the interrupt. In such a situation, system performance may be enhanced by waiting a predetermined time before actually instructing the microprocessor to interrupt execution of its current operation and effect a "hot restart" of the system.
Typically, a timeout circuit is implemented using some type of binary counter. In designing binary counter timeout circuits, two design parameters of low cell count and high granularity compete with each other. Low cell count refers to the desire to minimize the number of combinatorial logic gates when implementing the circuit, and high granularity refers to the ability of a timeout circuit to issue a timeout signal within exceedingly small time intervals.
When designing a timeout circuit using a binary counter, however, higher granularity is often obtained only at the expense of adding more combinatorial logic to the circuit. Accordingly, it is an object of the present invention to provide a timeout mechanism which maximizes granularity while minimizing combinatorial logic. It is a further object of the invention to implement such a timeout mechanism using a programmable linear feed back shift register instead of a binary counter.